Electrostatic discharges (ESDs) from human handling of a metal-oxide semiconductor (MOS) IC chip, or from other causes, permanently damage the IC chip. Often the thin-oxide layer that isolates the gate electrode from the substrate of a MOS field effect transistor is irreparably ruptured by a voltage spike applied across it. A voltage spike or ESD is often applied to the gate, because the gate electrode is connected to an external terminal or pin of the IC chip. The external terminals are formed on an input or output pad. To prevent such damage from excessive electrostatic discharges, a protective device is often connected between the pad and the internal circuits.
As CMOS technology is scaled down into submicron regime, the processes and the structures, such as a thinner gate oxide, shorter channel length, shallower source/drain junction, LDD (Lightly-Doped Drain) structure, and silicided diffusion, greatly degrade the ESD robustness of submicron CMOS ICs. Submicron CMOS devices, such as short channel thin-oxide MOS devices, are extremely susceptible to ESD damage. Therefore, ESD protection has become one of the most important elements with respect to the reliability of submicron CMOS ICs.
An NMOSFET is a very effective ESD protection device. Specifically, NMOS devices, either with the gate grounded (GGNMOS) or with the gate coupled to the positive ESD transient voltage (GCNMOS), have been commonly used as primary ESD protection elements for integrated circuits.
GGNMOS or GCNMOS can be used as the primary ESD protection element for ESD protection of an input pin. The input pad is connected to the drain of the NMOS, whose gate is either grounded or coupled to the drain and VSS by a capacitor and a resistor. The drain of the NMOS transistor is then connected to a series resistor of the order of 200 ohms, and then a secondary ESD protection element (say, a smaller GGNMOS) before connected to the first input gate.
In one application, an NMOS is used as the pull down transistor of a CMOS buffer to drive an output voltage for an external device. In this type of application, the gate of the NMOS is connected to an output driving signal.
In another common NMOS application, the gate is electrically connected to ground, and the NMOS is used as an ESD protection device for an input pin or a power bus during an ESD event.
The ESD protective action of an NMOS is based on the device's snap-back mechanism, which enables the NMOS to conduct a high level of ESD current between its drain and source. This occurs when a strong electric field across the depletion region in the drain substrate junction becomes high enough to begin avalanche breakdown, which in turn causes impact ionization, resulting in the generation of both minority and majority carriers. The minority carriers flow toward the drain contact, and the majority carriers flow toward the substrate/p-well contact, causing a local potential build up across the current path in the p-well substrate. When the local substrate potential is 0.6 V higher than an adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction then injects minority carriers (electrons) into the p-well, and these carriers eventually reach the drain junction to further enhance the impact ionization effect (see "ESD in Silicon Integrated Circuits", by A. Amerasekera and C. Duvvury, Chap. 3, Sec. 1., John Wiley & Sons, 1995). Eventually, the NMOS reaches a low impedance (snap-back) state, which enables it to conduct a large amount of ESD current.
To enhance the ESD protection capabilities of a MOSFET device, it is desirable to have a rapid turn on with a high degree of uniformity throughout the device. A known technique for accomplishing this objective utilizes a multi-gate-finger configuration to increase the gate effectiveness. However, in a typical multi-gate-finger NMOS structure, as shown in FIGS. 1 and 2, not all the poly gate fingers may turn on during an ESD event. That is, when the first few gate fingers reach their snap-back low impedance mode, the drain terminal to source terminal voltage is reduced to a value, called the snap-back voltage, which is less than the trigger voltage of the NMOS device. This has the effect of preventing the remaining gate fingers from being turned on. As a result, only a partial number of the gate fingers are available to absorb the ESD energy. Therefore, the ESD protection provided by the NMOS is significantly reduced.
When a MOSFET gate finger is triggered during an ESD event, the entire finger turns on. This is due to the cascading effect of the previously described impact ionization and snap-back process along the entire gate finger. Moreover, experimental data indicates that a long-gate-finger structure (e.g. 100 um.times.2), as shown in FIG. 4, has better ESD performance than a short-gate-finger structure (e.g. 20 um.times.10), of the type shown in FIG. 1, where both structures have the same total gate width of 200 um. That is, during an ESD event, the long-finger NMOS structure will have either one or two gate fingers (50% to 100% of total gate width) turned on, while the short-finger NMOS may only have a few fingers (out of 10) turned on, with each finger being only 10% of the total gate width, thus reducing the short-finger MOSFET's ability to absorb ESD current as compared to the long finger configuration. For manufacturing purposes, however, layout area is typically at a premium, and a conventional long-finger structure may not fit in the designated layout area. Therefore, both multi-gate-finger (short) and long-gate-finger (long) types of structures are used, depending on physical and electrical priorities.
A commonly used multi-gate-finger structure is shown in FIG. 4, where the poly-gate fingers are connected by a poly-gate bus, rather than the metal bus of FIG. 1.
One prior art technique for improving the uniform turn on of such a multi-gate-finger NMOS structure uses a gate coupled technique, as shown in FIG. 5, and as described in "ESD in Silicon Integrated Circuits", by A. Amerasekera and C. Duvvury, Chap. 4, Sec. 2., John Wiley & Sons, 1995. In this configuration, the drain is connected to either VDD or the buffer output line, and the gate is coupled to the drain via a capacitor C, and is also connected to ground via a resistor R. The coupling capacitor C and the RC time constant of the circuit cause the gate potential to rise to 1 to 2 V during the first 5 to 10 ns of an ESD event. The positive gate voltage reduces the triggering threshold of the NMOS, thereby enabling a more uniform turn-on of the gate fingers. However, improving the uniformity of the turn-on state of each finger is desirable.